Design Verification Engineer at Apple in Cupertino, California

Posted in Other 1 day ago.

Type: Full Time





Job Description:

Summary Posted: Jul 21, 2022 Role Number:200228229 Imagine what you could do here at Apple! New ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Do you love working on challenges that no one has solved yet? Bring passion and dedication to your career, and there's no telling what you could accomplish. Our Display Technologies Engineering team is working on the next generation of groundbreaking products using best in class tools, flows and methodologies. Come join our team and be a part of the excitement! Key Qualifications Coding experience in SystemVerilog or Verilog Knowledge of standard ASIC design and verification flows including RTL design, simulation and testbench development Solid problem solving skillset Experience with constrained random testing is a plus Knowledge of a HVL methodology like UVM/OVM is a plus Experience defining coverage space and writing coverage model is a plus Experience with SystemVerilog Assertion (SVA) is a plus Description As part of the verification team supporting Apple's Display Technologies portfolio for the next-generation of Apple products, you will work closely with Design and Architecture teams to review specifications and architecture, extract features and define verification plan including the coverage model. You will then execute on this plan through testbench development, directed/constrained random test generation, assertion-based verification, failure analysis and resolution, and coverage analysis and closure. You will run RTL and gate level functional simulations. You will also have the opportunity to support scripted automation flows to enhance the verification methodology. Education & Experience BSEE/BSCE + 3 years of relevant experience or MSEE/MSCE Additional Requirements PDN-9752756b-2594-4932-af15-2e0e1f5b7ad1


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