PDV CAD Engineer at Apple in Cupertino, California

Posted in Other 2 days ago.

Type: Full Time





Job Description:

Summary Posted: Sep 20, 2022 Role Number:200340527 Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and runset development for various technology nodes and tool sets. Working alongside the CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Also you should have worked with Dummy Metal Fill generation and Design for Manufacturability (DFM) rules at different technologies. Key Qualifications Typically requires 5-10 years of industry experience in Silicon chip design flows. Expertise in Calibre/ICV runset coding for DRC/LVS/ERC/MFILL is required. Rule coding in PERC is a plus. Tapeout support and SOC chip level PDV debug experience in various technology nodes is desirable. Scripting skills in programming languages such as Perl, Python, Tcl, Shell, Makefile and C. Understandings of Silicon technology. Knowledge of PnR tools, LEF/DEF, parasitic extraction is a plus. Description - Develop, maintain and improve all aspects of physical verification flow and methodology - Work with the chip integration/PD teams to facilitate SOC chip design process - Coordinate the effort of validating flows, improving for custom checks and data generation - Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs - Collaborate with tool vendors and foundries for PDK performance enhancements Education & Experience - BS/MS in EE/CS/CE or equivalent Additional Requirements PDN-9583c7b3-d1ec-4fc8-b07a-2bacd1ee338b


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