SOC Verification Engineer at Apple in Cupertino, California

Job Description:

Summary Posted: Sep 28, 2022 Role Number:200201783 Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. The SOC Verification Engineer will be responsible for pre-silicon RTL verification of block and top level SOC. With deep understanding of SOC architecture and meticulous attention to details, you will interact with all disciplines to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification. Key Qualifications 5+ years SOC verification experience. Expertise in HVL and HDL (SystemVerilog, Verilog). Advanced knowledge of HVL methodology (UVM/OVM/VMM). Solid verification skills in problem solving, constrained random testing, and debugging. Solid understanding of reusable verification framework. Knowledge of industry standard interfaces. Experience with System Verilog Assertion (SVA). Programing experience in C. Experience writing scripts in languages such as Perl or Python a plus. Programming experience in C++ and assembly a plus. Experience defining coverage space and writing coverage model a plus. Experience with low power verification is a plus. Should be a great teammate with excellent communication skills and the desire to take on diverse challenges. Experience with formal verification tool (JasperGold or others) is not required, but will be a huge plus. Description - Understand details of microarchitecture and build block / chip level testbench using best-in-class verification methodology. - Create verification plan from specification and in coordination with architects. - Generate directed and ingenuous constrained random tests. - Create/analyze coverage model and enhance testbench/test to increase coverage. - Build automated flows for block and chip level verification. - Debug failures, manage bug tracking, and close coverage. - Hold detailed verification reviews and set standard for coding quality. - Work closely with team members to improve methodology and flow. Education & Experience Typically requires MSEE or beyond. Additional Requirements Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. PDN-93c9213b-03e2-42a5-8abf-2d05f4a799dd