Physical Design VLSI, CAD Engineer (Early Career) at Apple in Santa Clara, California

Job Description:

Summary Posted: Oct 4, 2022 Role Number:200383960 As part of the Hardware Technology CAD team, you'll help design our next-generation, high-performance, power-efficient SoCs. You will work on world class CPU, GPU, analog/mixed signal and SOC designs by developing flows, tools and methodologies for future Apple products. You will work on exploring and enabling new technology nodes, stdcells and tools for design teams. You will contribute to improving design methodology using your understanding of CAD algorithms and ML to drive improvements in PPA (Power, Performance, Area) and design productivity and work closely with design and tool vendors to solve PPA challenges! We are looking for strong engineers to join our CAD team. In this role, you will be impacting a wide range of chips used across Apple's world-class products (iPhone, iPad, Mac, Apple Watch, Airpods...)! Key Qualifications Coursework or prior experience in VLSI Digital Integrated Circuits and flows. Understanding of physical design flows - Floorplanning, Power distribution, Placement, Clocking, Routing, Optimization Understanding of fundamental VLSI design concepts of timing and power Programming in one or more scripting language - Perl, Python, Tcl Self-motivator with strong problem-solving skills Great organizational skills, clear communication and teamwork skills. Understanding of standard formats of SDC constraints, power intent, parasitic files is a plus. Understanding of analysis flows such as timing analysis, physical verification etc is a plus. Description You will apply your hand-on skills developing, improving and supporting the implementation flow from RTL through GDS sign-off Primary responsibilities will include: Developing and supporting the implementation flow Developing and maintaining custom CAD tools for implementation and signoff Developing flow for new technology enablement Developing ML based flows for better PPA and productivity Collaborating with other tools like Physical Design Verification, RC extraction, IR and Static Timing analysis (STA) Improving methodology for place and route quality and turn around time (TAT) improvement Working with tool vendors to resolve tool/flow issues Education & Experience BS/MS/PhD Degree in technical field Additional Requirements PDN-96631658-b070-4b13-808f-c13ed1479c32