VLSI CAD Engineer - Noise and Timing for Gate-Level Flows and Methodologies at Apple in Cupertino, California

Job Description:

Summary Posted: Oct 4, 2022 Role Number:200252538 Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices! In this critical role, you will be responsible for defining, implementing, and supporting the methodologies, flows, and tools necessary to ensure clean noise and timing analysis for Apple silicon. As a CAD engineer working on noise and timing verification, you will work closely with design teams and CAD groups to ensure that our designs meet noise and performance goals. Key Qualifications The ideal candidate will have 5+ years of experience working in an EDA/CAD tool development/support role with hands-on experience in noise and STA flows. Familiarity with all aspects of noise and static timing analysis of large high-performance SoC or Processor designs in deep sub-micron technologies. Proficiency in analysis, tools, and methodologies for noise and timing closure. Good understanding of cross-talk, OCV effects, margins, and constraints. Programming in Perl, Python, Tcl, or other languages is a must. Good communicator who can accurately assess and describe issues to management and follow solutions through to completion. Familiarity with noise and timing ECO techniques and implementation is a plus. Familiarity with circuit modeling including SPICE models is a plus. Familiarity in distributed/scalable software development life cycles, including documentation and testing. Description In this exciting role on our team, you will: - Define consistent analysis methodology, margins, and perform tool validation for noise and timing verification. - Write and support flows and tools around core gate-level noise and static timing analysis tools. Conduct deep analysis of noise violations and timing paths to identify key issues. - Partner with design teams to understand and debug issues related to constraints, flow scripts, noise, and timing closure. - Facilitate and drive noise and STA methodology changes to improve overall flows. - Implement infrastructure/scripts to facilitate large scale noise and timing reports mining and visualization. - Help create noise and timing ECO custom scripts for project tapeout. - Work with Physical Design team, highlighting issues and best practices. - Create documentation and help with guidelines/specs. Education & Experience MS or BS Degree in a technical field Additional Requirements PDN-9425c265-2ed8-4bb5-bc71-f45c7d1ea401