The Role : Candidate will be responsible for FPGA implementation and create comprehensive functional test plans for the interface validation of IO controllers. The candidate will execute functional test plans of IP using FPGA hardware & software validation tools, oscilloscopes, & logic analyzers.
The Person : Requires good written and oral communication skills with a Demonstrated ability to communicate with a variety of engineering disciplines and management.
Responsibilities :
- FPGA implementation/timing closure using Xilinx Vivado tools
- Creating simple unit level test bench
- Pre silicon validation via FPGA for emulating the targeted IP sub-system
- Post silicon validation, lab bring up and debug of the targeted IP sub-system
- Root cause analysis and resolving issues encountered either in pre-silicon or post silicon targeted IP sub-system
Preferred Experience & Skill Set: • Requires experience and demonstrated technical expertise in the development & execution of platform level functional test plans. Platform level experience with high speed I/O interfaces • Experienced in FPGA development, Synthesis with logical & physical constraints, Timing closure and Place and Route in FPGA • Requires experience and demonstrated technical expertise in the domain of High speed I/O interfaces of computer system. • Requires good written and oral communication skills; Demonstrate the ability to communicate with a variety of engineering disciplines and management.
? Familiarity with Xilinx reference platforms such as Zynq reference board etc
EDUCATION: B. S. in Electrical Engineering or Computer Engineering