Location: 2600 Great America Way, Santa Clara, California, 95054
Position Title: Senior Engineer Design Enablement
Hours: Monday â€" Friday, 8:00 am to 5:00 pm
Summary of Duties:
Perform research and development work in Design and Technology co-optimization team, involving circuit design, timing methodologies, foundation intellectual properties (IP), stdcell library, memories and analog blocks in Advanced Technologies (22FDSOI, FinFET). Responsible for timing characterization and circuit design simulation verification. Perform and guide layout, and architect standard cells design.
Qualifications Position requires a PhD in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field of study. Alternately, will accept a Masterâ€™s degree in Electrical Engineering, Computer Engineering, or a closely related field of study, plus two (2) years of experience in the job offered, or in a related design engineering role. Requires knowledge or experience in CAD tools and scripting in Perl, Python, SKILL, TCL, C, and C++. Requires knowledge or experience in logic design, simulation and functional verification. Requires knowledge or experience in library characterization, view generation and validation. Requires knowledge or experience in performing SOC level planning and place and route. Requires knowledge of or experience with advanced technologies and PDKs. Requires knowledge or experience in Device and Transistor Bias schemes. Knowledge or experience can be gained concurrently through co-op, internship, or graduate degree curriculum.
GLOBALFOUNDRIES is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, gender identity, national origin, disability, or protected Veteran status.