Front-End Methodology CAD Engineer - RTL Lint at Apple in Beaverton, Oregon

Job Description:

Summary Posted: Jul 29, 2022 Role Number:200380906 Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices! As a Front-End Methodology CAD Engineer, you will play a major role in promoting a reliable work environment for developing, maintaining and improving our RTL and Gate Lint applications for our SoCs across multiple design sites. In addition, you will have the opportunity to write and support automation software for Connectivity and Hazard Checkers, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) applications that teams use to analyze RTL. Key Qualifications Typically requires at least 1 to 2 years of relevant experience. Expertise in TCL and/or PERL is required. Expertise in Verilog and System Verilog is required. Experience in RTL, Gate and DFT Lint solutions. Excellent communication, debug and root causing skills. Evangelize best practices in software development, testing and regression infrastructure. Source control system management (Perforce, Git). Experience in developing software framework or flows is a plus. Experience in Clock-Domain-Crossing (CDC) methodologies and Reset-Domain-Crossing (RDC) solutions is a plus. Description In this highly visible role, you will be: - Responsible for developing, maintaining and enhancing our Lint application for our SoCs across multiple design sites - Responsible for developing, maintaining and enhancing our Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) applications for our SoCs across multiple design sites - Apply your debugging experience to debug vendor tool problems and collaborate with designers to help solve their problems - You will work closely with EDA vendor representatives to drive improvements and new methodologies - You will participate in the automation of project creation and version control system work flows Education & Experience MS/BS Degree in technical field Additional Requirements PDN-96d3b85b-1739-4995-83d4-bf89da348cd5