Hiring a SoC Architect at an innovative start-up who are looking to develop cutting-edge computing platforms through hardware/software co-design, revolutionizing the industry with state-of-the-art technologies.
Your role will involve defining the architecture specification for the memory subsystem and determining its performance, power, and area requirements. Collaboration with internal software (e.g., OS, Kernel, FW), system (e.g., Board, Package, Power, Security), and silicon (e.g., RTL, DV, PD, Perf, DFT) team members, as well as industry consortia like JEDEC, will be integral to your responsibilities.
Requirements:
Proficiency in one or more of the following areas: memory subsystem design, cache memory, LPDDR/DDR/HBM/CXL memory.
Familiarity and experience with common performance benchmarks and workloads.
Understanding of fabric interconnect protocols like ARM AXI and CHI.
Ability to effectively collaborate within a team and meet aggressive deadlines.
Strong communication, influencing, and interpersonal skills to work collaboratively.
Proficiency in System Verilog, C or C++, and scripting languages such as Python.
Knowledge of high-level simulators for performance or power estimation is advantageous.
Experience with server-class memory systems, including familiarity with reliability requirements and ECC algorithms, is a bonus.
Familiarity with working with memory vendors and practical constraints related to capacity, bandwidth, and power is a plus.
Responsibilities:
Define memory subsystem requirements, including Power, Performance, Area (PPA), Reliability, Availability, Serviceability (RAS), Quality of Service (QoS), Security, and Debug.
Actively participate and contribute to industry-standard work groups such as JEDEC, CXL, and UCIe.
Collaborate with external memory and IP vendors on technical aspects of memory products.
Contribute to the microarchitecture specification of low latency and high bandwidth memory and cache controllers.
Conduct technical investigations, including Design Verification (DV) and Performance (Perf) analysis, in pre-silicon simulation and post-silicon validation.
Minimum Education & Experience:
Bachelor's degree with at least 5 years of industry experience.
Master's degree with at least 3 years of industry experience.